JPH0469814B2 - - Google Patents

Info

Publication number
JPH0469814B2
JPH0469814B2 JP61049912A JP4991286A JPH0469814B2 JP H0469814 B2 JPH0469814 B2 JP H0469814B2 JP 61049912 A JP61049912 A JP 61049912A JP 4991286 A JP4991286 A JP 4991286A JP H0469814 B2 JPH0469814 B2 JP H0469814B2
Authority
JP
Japan
Prior art keywords
silicon layer
region
polycrystalline silicon
semiconductor device
getter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61049912A
Other languages
English (en)
Japanese (ja)
Other versions
JPS62208638A (ja
Inventor
Jiro Ooshima
Tosho Ito
Tatsuichi Ko
Masaharu Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP61049912A priority Critical patent/JPS62208638A/ja
Priority to US07/020,758 priority patent/US4766086A/en
Publication of JPS62208638A publication Critical patent/JPS62208638A/ja
Publication of JPH0469814B2 publication Critical patent/JPH0469814B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Transistors (AREA)
  • Formation Of Insulating Films (AREA)
JP61049912A 1986-03-07 1986-03-07 半導体装置の製造方法 Granted JPS62208638A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP61049912A JPS62208638A (ja) 1986-03-07 1986-03-07 半導体装置の製造方法
US07/020,758 US4766086A (en) 1986-03-07 1987-03-02 Method of gettering a semiconductor device and forming an isolation region therein

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61049912A JPS62208638A (ja) 1986-03-07 1986-03-07 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JPS62208638A JPS62208638A (ja) 1987-09-12
JPH0469814B2 true JPH0469814B2 (en]) 1992-11-09

Family

ID=12844223

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61049912A Granted JPS62208638A (ja) 1986-03-07 1986-03-07 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US4766086A (en])
JP (1) JPS62208638A (en])

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4877748A (en) * 1987-05-01 1989-10-31 Texas Instruments Incorporated Bipolar process for forming shallow NPN emitters
US5289031A (en) * 1990-08-21 1994-02-22 Kabushiki Kaisha Toshiba Semiconductor device capable of blocking contaminants
JPH06104268A (ja) * 1992-09-21 1994-04-15 Mitsubishi Electric Corp ゲッタリング効果を持たせた半導体基板およびその製造方法
JP3024409B2 (ja) * 1992-12-25 2000-03-21 日本電気株式会社 半導体装置の製造方法
JPH06252153A (ja) * 1993-03-01 1994-09-09 Toshiba Corp 半導体装置の製造方法
JP3384506B2 (ja) * 1993-03-30 2003-03-10 ソニー株式会社 半導体基板の製造方法
JP2783123B2 (ja) * 1993-05-28 1998-08-06 日本電気株式会社 半導体基板およびその製造方法
JPH09120965A (ja) * 1995-10-25 1997-05-06 Toshiba Corp 半導体装置の製造方法
JP2943728B2 (ja) * 1996-10-18 1999-08-30 日本電気株式会社 半導体装置の製造方法
US5994207A (en) 1997-05-12 1999-11-30 Silicon Genesis Corporation Controlled cleavage process using pressurized fluid
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
EP1939932A1 (en) 1999-08-10 2008-07-02 Silicon Genesis Corporation A substrate comprising a stressed silicon germanium cleave layer
WO2001023649A1 (fr) * 1999-09-29 2001-04-05 Shin-Etsu Handotai Co., Ltd. Tranche, filtre epitaxial et leur procede de fabrication
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
US6576501B1 (en) * 2002-05-31 2003-06-10 Seh America, Inc. Double side polished wafers having external gettering sites, and method of producing same
JP4534412B2 (ja) * 2002-06-26 2010-09-01 株式会社ニコン 固体撮像装置
US7470944B2 (en) * 2002-06-26 2008-12-30 Nikon Corporation Solid-state image sensor
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
US20140253169A1 (en) * 2013-03-07 2014-09-11 International Business Machines Corporation Burst noise in line test

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2191272A1 (en]) * 1972-06-27 1974-02-01 Ibm France
JPS5052969A (en]) * 1973-09-06 1975-05-10
DE2449688C3 (de) * 1974-10-18 1980-07-10 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung einer dotierten Zone eines Leitfähigkeitstyps in einem Halbleiterkörper
US4063973A (en) * 1975-11-10 1977-12-20 Tokyo Shibaura Electric Co., Ltd. Method of making a semiconductor device
US4133704A (en) * 1977-01-17 1979-01-09 General Motors Corporation Method of forming diodes by amorphous implantations and concurrent annealing, monocrystalline reconversion and oxide passivation in <100> N-type silicon
US4389255A (en) * 1980-01-14 1983-06-21 Burroughs Corporation Method of forming buried collector for bipolar transistor in a semiconductor by selective implantation of poly-si followed by oxidation and etch-off
US4322882A (en) * 1980-02-04 1982-04-06 Fairchild Camera & Instrument Corp. Method for making an integrated injection logic structure including a self-aligned base contact
JPS57187941A (en) * 1981-05-14 1982-11-18 Nec Corp Manufacture of semiconductor substrate
US4437897A (en) * 1982-05-18 1984-03-20 International Business Machines Corporation Fabrication process for a shallow emitter/base transistor using same polycrystalline layer
DE3330895A1 (de) * 1983-08-26 1985-03-14 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von bipolartransistorstrukturen mit selbstjustierten emitter- und basisbereichen fuer hoechstfrequenzschaltungen
US4640721A (en) * 1984-06-06 1987-02-03 Hitachi, Ltd. Method of forming bipolar transistors with graft base regions

Also Published As

Publication number Publication date
JPS62208638A (ja) 1987-09-12
US4766086A (en) 1988-08-23

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